Curriculum Vitae

Education

• Ph.D in Electrical and Computer Engineering
  University of Illinois at Urbana-Champaign (UIUC), US, 2023
• M.S. in Electrical and Computer Engineering
  University of Illinois at Urbana-Champaign (UIUC), US, 2020
• B.S. in Computer Engineering
  University of Illinois at Urbana-Champaign (UIUC), US, Highest Honor, 2017
• B.S. in Applied Mathematics
  University of Illinois at Urbana-Champaign (UIUC), US, High Distinction, 2017

Work experience

• May 2026-present: Assistant Professor at Department of Design Automation and Computing System, School of Integrated Circuits, Peking University

• Feb 2023-April 2026: Principal Engineer at Design Automation Lab, Hong Kong Research Center (currently Leibniz Research Center), Huawei
  • Duties: Responsible for hierarchical and parallelized static timing analysis frameworks, and parallelization algorithms in logic synthesis and physical design flows
• May 2022-August 2022: Senior Software Engineer Intern in Logic Synthesis Group, Cadence Inc.
  • Duties: Research and develop a fast parallel programming framework for timing analysis in logic synthesis
• May 2021-August 2021: Senior Hardware Engineer Intern in Timing Group, IBM
  • Duties: Research and develop new parallelization framework for deterministic timing analysis
• May 2019-August 2019: Software Development Engineer Intern in Physical Design Group, Cadence Inc.
  • Duties: Research and develop a dynamic task-based multithreading model for Maze Routing
• August 2017-Dec 2022: Graduate Research Assistant
  • Duties: Research on Static Timing Analysis (STA) and heterogeneous acceleration on EDA algorithms.
  • Supervisor: Professor Martin D.F. Wong
• August 2017-Dec 2022: Graduate Teaching Assistant, Artificial Intelligence (ECE 448) and GPU programming (ECE 408), UIUC
  • Duties: Design machine problems and exams, organize course content, hold office hours, participate in various grading activities, and provide technical answers in the class forum
• Jan 2016-Dec 2016: Undergraduate Teaching Assistant, Computer System Engineering (ECE 391), UIUC
  • Duties: Hold office hours, participate in various grading activities, and present course material
• May 2016-August 2016: Undergraduate Research Assistant
  • Duties: Research on an automated algorithm to solve simultaneous escape routing problem with SAT solver
  • Supervisor: Professor Martin D.F. Wong

Publications

Efficient and Effective E-graph-based Logic Optimization

GraphCAD: Leveraging Graph Neural Networks for Accuracy Prediction Handling Crosstalk-affected Delays

Ink: Efficient Incremental k-Critical Path Generation

GCS-Timer: GPU-Accelerated Current Source Model Based Static Timing Analysis

A GPU-Accelerated Framework for Path-Based Timing Analysis

Fast STA Graph Partitioning Framework for Multi-GPU Acceleration

Cpp-Taskflow: A General-purpose Parallel Task Programming System at Scale

OpenTimer v2: A New Parallel Incremental Timing Analysis Engine

GPU-accelerated Path-based Timing Analysis

GPU-accelerated Critical Path Generation with Path Constraints

An Efficient Critical Path Generation Algorithm Considering Extensive Path Constraints

Essential Building Blocks for Creating an Open-source EDA Project

Cpp-Taskflow: Fast Task-based Parallel Programming using Modern C++

An Efficient and Composable Parallel Task Programming Library

A Modern C++ Parallel Task Programming Library

MtDetector: A High-performance Marine Traffic Detector at Stream Scale

A General-purpose Distributed Programming System using Data-parallel Streams

Teaching

Teaching experience TBD